Wenji Fang
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Paper-Conference
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
Feb 15, 2025
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
Feb 14, 2025
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
Feb 14, 2025
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
Jan 22, 2025
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
Jan 15, 2025
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Jan 15, 2025
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
Jan 15, 2025
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)
Jul 21, 2024
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
Feb 1, 2024
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Feb 1, 2024
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