Paper-Conference

SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models

Sep 1, 2025

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment

Jun 30, 2025

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Mar 29, 2025

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph

Feb 15, 2025

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits

Feb 14, 2025

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

Feb 14, 2025

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

Jan 22, 2025

Profile-Guided Temporal Prefetching

Jan 20, 2025

Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage

Jan 15, 2025

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs

Jan 15, 2025