Publications

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie (2025). Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. In ASP-DAC.

Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang (2025). AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. In ASP-DAC.

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2025). A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. In ASP-DAC.

Mengming Li, Wenji Fang, Qijun Zhang, Zhiyao Xie (2025). SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. In ISEDA.

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie (2025). Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. In TCAD.

Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie (2025). RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. In TCAD.

Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F.Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou (2024). Large circuit models: opportunities and challenges. In SCIS.

Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie (2024). OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited). In ICCAD.

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie (2024). RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. In LAD.

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2024). Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. In DAC.