Wenji Fang
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    • SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
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OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)

Jul 21, 2024·
Shang Liu
,
Yao Lu
Wenji Fang
Wenji Fang
,
Mengming Li
,
Zhiyao Xie
· 0 min read
Cite
Type
Conference paper
Publication
In International Conference of Computer-Aided Design
Last updated on Jul 21, 2024
Wenji Fang
Authors
Wenji Fang
PhD Student
← Large circuit models: opportunities and challenges Nov 1, 2024
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization Feb 1, 2024 →

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