Wenji Fang
  • Bio
  • Research
  • Publications
  • Experience
  • Awards
  • Teaching
  • Recent & Upcoming Talks
    • Example Talk
  • Publications
    • A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
    • NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
    • ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
    • SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
    • CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
    • Profile-Guided Temporal Prefetching
    • A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
    • AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
    • Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
    • SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
    • RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
    • Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques
    • Large circuit models: opportunities and challenges
    • OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)
    • Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
    • RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
    • MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
    • r-map: Relating Implementation and Specification in Hardware Refinement Checking
    • WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification
    • An Integrated Single-Shot Spectrometer With Large Bandwidth-Resolution Ratio and Wide Operation Temperature Range
  • Projects
  • Blog
    • 🎉 Easily create your own simple yet highly customizable blog
    • 🧠 Sharpen your thinking with a second brain
    • 📈 Communicate your results effectively with the best data visualizations
    • 👩🏼‍🏫 Teach academic courses
    • ✅ Manage your projects
  • Projects
    • Hardware Formal Verification
    • VLSI Design Quality Evaluation
    • Circuit Foundation Model
  • Experience
  • Teaching
    • Learn JavaScript
    • Learn Python
  • Publications
    • An example preprint / working paper
    • An example journal article
    • An example conference paper

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)

Jul 21, 2024·
Shang Liu
,
Yao Lu
Wenji Fang
Wenji Fang
,
Mengming Li
,
Zhiyao Xie
· 0 min read
Cite
Type
Conference paper
Publication
In International Conference of Computer-Aided Design
Last updated on Jul 21, 2024
Wenji Fang
Authors
Wenji Fang
PhD Student
← Large circuit models: opportunities and challenges Nov 1, 2024
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization Feb 1, 2024 →

© 2025 Me. This work is licensed under CC BY NC ND 4.0

Published with Hugo Blox Builder — the free, open source website builder that empowers creators.