Wenji Fang
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Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

Feb 1, 2024·
Wenji Fang
Wenji Fang
,
Shang Liu
,
Hongce Zhang
,
Zhiyao Xie
· 0 min read
PDF Cite Code
Type
Conference paper
Publication
In Design Automation Conference
Last updated on Feb 1, 2024
Wenji Fang
Authors
Wenji Fang
PhD Student
← Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques Jul 1, 2024
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design Jul 21, 2023 →

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