Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early OptimizationFeb 1, 2024ยทWenji Fang,Shang Liu,Hongce Zhang,Zhiyao Xieยท 0 min read PDF Cite CodeTypeConference paperPublicationIn Design Automation ConferenceLast updated on Feb 1, 2024 AuthorsWenji FangPhD Student ← OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited) Jul 21, 2024RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution Feb 1, 2024 →