Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL StageJan 15, 2025·Shang LiuWenji Fang,Yao Lu,Qijun Zhang,Zhiyao Xie· 0 min read CiteTypeConference paperPublicationIn Asia and South Pacific Design Automation Conference (ASP-DAC)Last updated on Jan 15, 2025 AuthorsWenji FangPhD Student ← AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs Jan 15, 2025RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique Jan 1, 2025 →
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