Wenji Fang
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    • A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
    • AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
    • OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)
    • Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques
    • Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
    • MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
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    • WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification
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A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks

Sep 3, 2024·
Wenji Fang
Wenji Fang
,
Shang Liu
,
Hongce Zhang
,
Zhiyao Xie
· 0 min read
Cite
Type
Conference paper
Publication
In Asia and South Pacific Design Automation Conference (ASP-DAC)
Last updated on Sep 3, 2024
Wenji Fang
Authors
Wenji Fang
PhD Student
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs Sep 2, 2024 →

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