Publications

2026

ICCAD '26

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement

Wenji Fang, Yao Lu, Shang Liu, Jing Wang, Ziyan Guo, Junxian He, Fengbin Tu, Zhiyao Xie

ICCAD '26

E-Layout: Layout-Stage Restructuring via RL-Optimized Equality-Saturated Graph Retrieval-Augmented Generation

Wenji Fang, Rongjian Liang, Yi-Chen Lu, Cunxi Yu, Chen Chen, Shang Liu, Chenhui Deng, Wenkai Li, Haoxing Ren, Zhiyao Xie

ICCAD '26

AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications

Yuchao Wu^*, Wenji Fang^*, Jing Wang, Wenkai Li, Ziyan Guo, Zhiyao Xie

ICCAD '26

CorrectRTL: Boost RTL Generation Quality Through Automated Self-Correction with Instruction Decomposition

Jing Wang, Shang Liu, Hangan Zhou, Wenji Fang, Yuchao Wu, Yugao Zhu, Zhiyao Xie

TODAES '26

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Wenji Fang^*, Jing Wang^*, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie

DAC '26

COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging

Yao Lu, Zhicheng Guo, Qijun Zhang, Ziyan Guo, Shang Liu, Wenji Fang, Wenkai Li, Zhiyao Xie

DAC '26

LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power

Wenkai Li, Yuchao Wu, Ziyan Guo, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie

DAC '26

RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

Ziyan Guo, Wenji Fang, Wenkai Li, Yuchao Wu, Shang Liu, Zhiyao Xie

TCAD '26

A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis

Wenkai Li, Yao Lu, Wenji Fang, Yugao Zhu, Ziyan Guo, Jing Wang, Mengming Li, Qijun Zhang, Zhiyao Xie

TCAD '26

MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension

Yugao Zhu, Wenji Fang, Yao Lu, Shang Liu, Yanzhen Zhu, Qijun Zhang, Zhiyao Xie

2025

EMNLP '25

SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models

Shang Liu, Yao Lu, Wenji Fang, Jing Wang, Zhiyao Xie

ICCAD '25

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment

Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Zhiyao Xie

DAC '25

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph

Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie

[code] [pdf] [poster] [slides]

DAC '25

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie

DAC '25

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits

Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie

ICLR '25

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie

[code] [pdf] [poster] [slides]

ISCA '25

Profile-Guided Temporal Prefetching

Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie

ASP-DAC '25

A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie

[code] [pdf] [slides]

ASP-DAC '25

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs

Zhiyuan Yan^*, Wenji Fang^*, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang

ASP-DAC '25

Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie

ISEDA '25

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model

Mengming Li, Wenji Fang, Qijun Zhang, Zhiyao Xie

TCAD '25

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique

Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie

TCAD '25

Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie

2024

SCIS '24

Large circuit models: opportunities and challenges

Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F.Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou

ICCAD '24

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)

Shang Liu^*, Yao Lu^*, Wenji Fang^*, Mengming Li, Zhiyao Xie

DAC '24

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie

[code] [pdf] [poster] [slides]

LAD '24

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie

2023

ICCAD '23

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie

[code] [pdf] [poster] [slides]

TCAD '23

r-map: Relating Implementation and Specification in Hardware Refinement Checking

Wenji Fang, Guangyu Hu, Hongce Zhang

TACAS '23

WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification

Wenji Fang, Hongce Zhang

[pdf] [code] [slides] [video]

PhotoniX '23

An Integrated Single-Shot Spectrometer With Large Bandwidth-Resolution Ratio and Wide Operation Temperature Range

Ang Li, Chang Wang, Feixia Bao, Wenji Fang, Yuxin Liang, Rui Cheng, Shilong Pan