Publications

Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie (2025). A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA. Under Review.

Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie (2025). NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. In DAC.

Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie (2025). SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. In DAC.

Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie (2025). ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. In DAC.

Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie (2025). CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. In ICLR.

Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie (2025). Profile-Guided Temporal Prefetching. In ISCA.

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie (2025). Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. In ASP-DAC.

Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang (2025). AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. In ASP-DAC.

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2025). A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. In ASP-DAC.

Mengming Li, Wenji Fang, Qijun Zhang, Zhiyao Xie (2025). SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. In ISEDA.