Publications

Wenkai Li, Yao Lu, Wenji Fang, Yugao Zhu, Ziyan Guo, Jing Wang, Mengming Li, Qijun Zhang, Zhiyao Xie (2026). A Self-Supervised and Cross-Design Netlist Power Model for Time-Based Layout Power Analysis. In TCAD.

Yugao Zhu, Wenji Fang, Yao Lu, Shang Liu, Yanzhen Zhu, Qijun Zhang, Zhiyao Xie (2026). MFSPart: A Generalized Partitioning Framework for Multi-FPGA Systems and Its Ensemble-Based Extension. In TCAD.

Shang Liu, Yao Lu, Wenji Fang, Jing Wang, Zhiyao Xie (2025). SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models. In EMNLP.

Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Zhiyao Xie (2025). GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment. In ICCAD.

Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie (2025). A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA. Under Review.

Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie (2025). NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. In DAC.

Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie (2025). SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits. In DAC.

Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie (2025). ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. In DAC.

Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie (2025). CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. In ICLR.

Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie (2025). Profile-Guided Temporal Prefetching. In ISCA.