Publications

(2025). NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. In DAC.
(2025). ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. In DAC.
(2025). CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. In ICLR.
(2025). Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. In ASP-DAC.
(2025). AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. In ASP-DAC.
(2025). Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. In TCAD.
(2025). RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. In TCAD.
(2024). Large circuit models: opportunities and challenges. In SCIS.