About Me
Hi! I’m Wenji Fang (方闻绩), a Ph.D. student at the Electronic and Computer Engineering Department of the Hong Kong University of Science and Technology, advised by Prof. Zhiyao Xie. Previously, I received my M.Phil from the Hong Kong University of Science and Technology (Guangzhou), advised by Prof. Hongce Zhang, and my B.Eng from Nanjing University of Aeronautics and Astronautics.
Interests
- AI for EDA
- Circuit Quality Evaluation
- Circuit Functional Verification
Education
PhD in Electronic and Computer Engineering
HKUST
MPhil in Microelectronics
HKUST(GZ)
BEng in Electrical Engineering and Automation
NUAA
Research Overview
Circuit Foundation Model
- Large Circuit Model [SCIS'24]
- RTL-netlist encoder alignment [ASPDAC'25].
VLSI Design Quality Evaluation
- RTL-stage fine-grained timing slack prediction [DAC'24]
- RTL-stage overall PPA prediction [TCAD'24]&[ICCAD'23]
Hardware Formal Verification
- LLM-aided assertion generation [ASPDAC'25]&[ICCAD'24]
- CPU Symbolic simulation [TACAS'23]&[TCAD'23]
First-Authored Publications
(2024).
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks.
In ASP-DAC.
(2024).
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
In ASP-DAC.
(2024).
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited).
In ICCAD.
Awards
- DAC Young Fellow, 2024
- ISLAD Best Paper Nomination, 2024
- ISLAD Travel Grant, 2024
- Full Postgraduate Studentship of HKUST, 2024-Now
- ICCAD Student Scholar Program Grant, 2023
- 3rd Place Award of EDAthon Contest, 2023
- Full Postgraduate Studentship of HKUST(GZ), 2022-2024
- Infineon Technology Scholarship, 2020
- First Class Scholarship of NUAA, 2017-2021
Teaching
- TA of MICS6000H Logic Design Automation of Digital Systems, HKUST(GZ)